2023

Energy-efficient Task Adaptation for NLP Edge Inference Leveraging Heterogeneous Memory Architectures

Z. Fu, A. Avaliani, M. Donato
ArXiv PDF

2022

A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

T. Tambe, E.-Y. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, G.-Y. Wei
JSSC

2021

Edgebert: Sentence-level energy optimizations for latency-aware multi-task NLP inference

T. Tambe, C. Hooper, L. Pentecost, T. Jia, E.-Y. Yang, M. Donato, V. Sanh, P. Whatmough, A. Rush, D. Brooks, G.-Y. Wei
MICRO54 PDF

SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators

S.K. Lee, P. Whatmough, M. Donato, G. Ko, D. Brooks, G-Y. Wei
JSSC PDF

NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories

L. Pentecost, A. Hankin, M. Donato, M. Hempstead, G-Y. Wei, D. Brooks
ArXiv PDF

Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories

M.M. Sharifi, L. Pentecost, R. Rajaei, A. Kazemi, Q. Lou, G-Y. Wei, D. Brooks, K. Ni, X. Hu, M. Niemier, M. Donato
ISLPED PDF

A 25mm² SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET

T. Tambe, E-Y. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, G-Y. Wei
ISSCC PDF

2020

A 3mm² Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm

G. Ko, Y. Chai, M. Donato, P. Whatmough, T. Tambe, R. Rutenbar, D. Brooks, G.-Y. Wei
IEEE Symposium on VLSI Circuits PDF

Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM

E. Rezaei, M. Donato, W. Patterson, A. Zaslavsky, and R. I. Bahar
IEEE Transactions on Device and Materials Reliability PDF

CHIPKIT: An agile, reusable open-source framework for rapid test chip development

P. Whatmough. M. Donato, G. Ko, D. Brooks, and G.-Y. Wei
IEEE MICRO PDF GitHub

2019

MaxNVM: Maximizing DNN storage density and inference efficiency with sparse encoding and error mitigation

L. Pentecost, M. Donato, B. Reagen, U. Gupta, S. Ma, G.-Y. Wei, and D. Brooks
MICRO52 PDF

MEMTI: Optimizing on-chip non-volatile storage for visual multi-task inference at the edge

M. Donato, L. Pentecost, D. Brooks, and G.-Y. Wei
IEEE MICRO PDF

MASR: A modular accelerator for sparse RNNs

U. Gupta, B. Reagen, L. Pentecost, M. Donato, T. Tambe, A. Rush, G.-Y. Wei, D. Brooks
PACT PDF

Fully-CMOS multi-level embedded non-volatile memory devices with reliable long-term retention for efficient storage of neural network weights

S. Ma, M. Donato, S. K. Lee, D. Brooks, and G.-Y. Wei
IEEE Electron Device Letters PDF

A 16nm 25mm² SoC with a 54.5x flexibility-efficiency range from dual-core Arm Cortex-A53, to eFPGA, and cache-coherent accelerators

P. Whatmough, S. K. Lee, M. Donato, H. C. Hsueh, S. Xi, U. Gupta, L. Pentecost, G. Ko, D. Brooks, and G.-Y. Wei
IEEE Symposium on VLSI Circuits PDF

2018

On-chip deep neural network storage with multi-level eNVM

M. Donato, B. Reagen, L. Pentecost, U. Gupta, D. Brooks, and G.-Y. Wei
DAC PDF

A sub-threshold noise transient simulator based on integrated random telegraph and thermal noise modeling

M. Donato, R. I. Bahar, W. R. Patterson, and A. Zaslavsky
Transactions on Computer-Aided Design PDF

2016 and earlier

A fast simulator for the analysis of sub-threshold thermal noise transients

M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky
DAC PDF

Design of error-resilient logic gates with reinforcement using implications

X. Han, M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky
GLSVLSI PDF

A simulation framework for analyzing transient effects due to thermal noise in sub-threshold circuits

M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky
GLSVLSI PDF

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

M. Donato, F. Cremona, W. Jin, R. I. Bahar, W. Patterson, A. Zaslavsky, and J. Mundy
GLSVLSI PDF

Shot-noise-induced failure in nanoscale flip-flops Part II: Failure rates in 10-nm ultimate CMOS

P. Jannaty, F. C. Sabou, S. T. Le, M. Donato, R. I. Bahar, W. Patterson, J. Mundy, and A. Zaslavsky
IEEE Transactions on Electron Devices PDF

Shot-noise-induced failure in nanoscale flip-flops Part I: Numerical framework

P. Jannaty, F. C. Sabou, S. T. Le, M. Donato, R. I. Bahar, W. Patterson, J. Mundy, and A. Zaslavsky
IEEE Transactions on Electron Devices PDF