About Me
I am an Assistant Professor of Electrical and Computer Engineering at Tufts University where I lead the TECS Lab. Before joining Tufts, I was a Research Associate in Harvard University’s John A. Paulson School of Engineering and Applied Sciences working in the Architecture, Circuits, and Compilers group.
I am looking for Ph.D. students! Please send me an email if you are interested.
My research broadly investigates design methodologies for energy-efficient and reliable hardware systems. I am currently working on co-design methodologies for building specialized architectures for machine learning applications that leverage dense, fault-prone embedded non-volatile memories.
I received my Ph.D. degree in Electrical Sciences and Computer Engineering from Brown University.
You can find my full CV here
Education
Brown University
Ph.D. in Electrical Sciences and Computer Engineering
2016
Università di Roma La Sapienza
M.Sc. in Electrical Engineering
2010
Università di Roma La Sapienza
B.Sc. in Electrical Engineering
2008
Publications
[1] T. Tambe, C. Hooper, L. Pentecost, T. Jia, E.-Y. Yang, M. Donato, V. Sanh, P. Whatmough, A. Rush, D. Brooks, G.-Y. Wei, “Edgebert: Sentence-level energy optimizations for latency-aware multi-task NLP inference”, in Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
[2] S.K. Lee, P. Whatmough, M. Donato, G. Ko, D. Brooks, G-Y. Wei, “SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators”, IEEE Journal of Solid-State Circuits (JSSC)
[3] L. Pentecost, A. Hankin, M. Donato, M. Hempstead, G-Y. Wei, D. Brooks, “NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories”
[4] M.M. Sharifi, L. Pentecost, R. Rajaei, A. Kazemi, Q. Lou, G-Y. Wei, D. Brooks, K. Ni, X. Hu, M. Niemier, M. Donato, “Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories” in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 2021
[5] T. Tambe, E-Y. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, G-Y. Wei, “A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET”, in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021
[6] G. Ko, Y. Chai, M. Donato, P. Whatmough, T. Tambe, R. Rutenbar, D. Brooks, G.-Y. Wei, “A 3mm^2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm” in IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2020
[7] E. Rezaei, M. Donato, W. Patterson, A. Zaslavsky, and R. I. Bahar, “Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM” IEEE Transactions on Device and Materials Reliability [pdf]
[8] P. Whatmough. M. Donato, G. Ko, D. Brooks, and G.-Y. Wei, “CHIPKIT: An agile, reusable open-source framework for rapid test chip development”, IEEE MICRO [pdf]
[9] M. Donato, L. Pentecost, D. Brooks, and G.-Y. Wei, “MEMTI: Optimizing on-chip non-volatile storage for visual multi-task inference at the edge”, IEEE MICRO, vol. 39, no. 6, Nov./Dec. 2019 [pdf]
[10] L. Pentecost, M. Donato, B. Reagen, U. Gupta, S. Ma, G.-Y. Wei, and D. Brooks, “MaxNVM: Maximizing DNN storage density and inference efficiency with sparse encoding and error mitigation” in Proceedings of the 52th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO52), Oct. 2019 [pdf]
[11] S. Ma, M. Donato, S. K. Lee, D. Brooks, and G.-Y. Wei, “Fully-CMOS multi-level embedded non-volatile memory devices with reliable long-term retention for efficient storage of neural network weights”, IEEE Electron Device Letters, vol.40, no.9, Sep. 2019
[12] U. Gupta, B. Reagen, L. Pentecost, M. Donato, T. Tambe, A. Rush, G.-Y. Wei, D. Brooks, “MASR: A modular accelerator for sparse RNNs”, in Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct. 2019
[13] E. Rezaei, M. Donato, W. Patterson, A. Zaslavsky, and R. I. Bahar, “Thermal noise-induced error simulation framework for subthreshold CMOS SRAM” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2019
[14] P. Whatmough, S. K. Lee, M. Donato, H. C. Hsueh, S. Xi, U. Gupta, L. Pentecost, G. Ko, D. Brooks, and G.-Y. Wei, “A 16nm 25mm^2 SoC with a 54.5x flexibility-efficiency range from dual-core Arm Cortex-A53, to eFPGA, and cache-coherent accelerators” in IEEE Symposium on VLSI Circuits (VLSIC), Jun. 2019 [pdf]
[15] M. Donato, B. Reagen, L. Pentecost, U. Gupta, D. Brooks, and G.-Y. Wei, “On-chip deep neural network storage with multi-level eNVM” in Proceedings of the 55th Annual Design Automation Conference (DAC), Jun. 2018 [pdf]
[16] M. Donato, R. I. Bahar, W. R. Patterson, and A. Zaslavsky, “A sub-threshold noise transient simulator based on integrated random telegraph and thermal noise modeling” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.37, no.3, 2018
[17] M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky, “A fast simulator for the analysis of sub-threshold thermal noise transients” in Proceedings of the 53rd Annual Design Automation Conference (DAC), Jun. 2016
[18] X. Han, M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky, “Design of error-resilient logic gates with reinforcement using implications” in Proceedings of the 26th Edition on the Great Lakes Symposium on VLSI (GLSVLSI), May 2016
[19] M. Donato, R. I. Bahar, W. Patterson, and A. Zaslavsky, “A simulation framework for analyzing transient effects due to thermal noise in sub-threshold circuits” in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI (GLSVLSI), May 2015
[20] M. Donato, F. Cremona, W. Jin, R. I. Bahar, W. Patterson, A. Zaslavsky, and J. Mundy, “A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic” in Proceedings of the 22th Edition on Great Lakes Symposium on VLSI (GLSVLSI), May 2012
[21] P. Jannaty, F. C. Sabou, S. T. Le, M. Donato, R. I. Bahar, W. Patterson, J. Mundy, and A. Zaslavsky, “Shot-noise-induced failure in nanoscale flip-flops Part I: Numerical framework” IEEE Transactions on Electron Devices, vol.59, no.3, 2012
[22] P. Jannaty, F. C. Sabou, S. T. Le, M. Donato, R. I. Bahar, W. Patterson, J. Mundy, and A. Zaslavsky, “Shot-noise-induced failure in nanoscale flip-flops Part II: Failure rates in 10-nm ultimate CMOS” IEEE Transactions on Electron Devices, vol.59, no.3, 2012