One of the most common kinds of flip-flops (or, just flops) is the
D-type flop. Like all flops, it has the ability to remember one bit of
digital information. What makes the D-flop special is that it is a
clocked flip-flop. We'll spend some time looking at what that means.
First, let's go through the pins of a standard D-flop. The diagram above is
for half of a 74HCT74 chip, which comes with two D-flops on one IC.
D is the Data Input pin. This is where the flop gets its information
Q is the Output pin. It shows what value the flop is currently
Q' is the Inverted Output pin. It shows the opposite of the value
that the flop is remembering.
CLK is the clock pin. When a new clock pulse comes in, the
flop checks the input pin D, and sets itself up to remember that input value.
The D-flop is edge-triggere, which means that it responds to the
rising edge of the clock pulse. This will be clearer when we look at a timing
R is an Active-LOW Reset pin. When the Reset pin gets a LOW signal,
it resets the flop to remember a 0, or LOW value.
S (also called PRE on some diagrams) is an Active-Low Set pin. When
it gets a LOW signal, it sets the flop to remember a 1, or HIGH value.
The flip-flop is the foundation of sequential logic. To
understand how to use flops, we need to see how they function over time in
reponse to different signals. We'll walk through a sequence,
using a timing diagram to help show what's going on.
At the beginning of the diagram, the inputs to the D and CLK pins are LOW,
and the Q output also happens to be LOW. At point A,
the D input goes HIGH.
However, since there is no clock pulse, the Q output does not change yet.
At point B, the CLK input sees a rising edge. That rising edge tells
the flop to remember the D input.
A very short time passes from point B to point C,
which is the time needed
to actually make the flop remember the new value. Note that now the Q output
is the same as the D input.
At point D, the D-input goes to LOW.
However, the Q output does not change,
because there is no clock pulse.
At point E, we have a falling edge on the CLK input. However,
our flop only responds to rising edges,
so the output Q still persists.
Note that the S and R pins will Set or Reset the flop regardless of the
D input or clock pulses. These pins are often used to set the flop to
an initial state before our logic circuits begin their work.
Here's the pinout of the 74HCT74N, a dual D-type flip-flop. Note that
the 'dual' designation means that two flops come on one chip.