Project Summary

Wireless networking has made significant inroads into the infrastructure of electronic commerce and consumer services in the past few years. A significant portion of this growth is in the area of wireless local area networks (WLAN). The predominant wireless LAN standard in the United States is the IEEE Std. 802.11 and its Addendums (particularly 802.11b, 802.11g, 802.11i and the upcoming 802.11n). The most common form of implementation of this WLAN functionality in products and embedded mobile devices is through the use of embedded microprocessor cores. Most WLAN products have some form of microprocessor running software for the 802.11 protocol, and providing interfacing to the device platform’s internal communication bus, memory, and other electronic hardware.

On the same time, there are increasing demands on the processing capability of microprocessor-based networking devices coming from three different sources: (1) the recent adoption and proliferation of MPEG- 4 video on demand services, thus requiring greater data compression capability; (2) the increased need to provide greater levels of security by data encryption over WLANs; and (3) the increased need to support higher levels of error correction over increasingly crowded and “noisy” wireless channels. This processing demand pushes the computing ability of standard microprocessors to their limits. It is for this reason—better computing throughput, and lower power consumption— that we are exploring an alternate hardware implementation strategy of creating the core functionality of the 802.11 WLAN protocol directly in silicon, rather than write software to program a microprocessor. This chip allows systems builders to create high-performance, low-power design solutions.

Our design focus on the VLSI implementation of the basic function of IEEE 802.11 receiver MAC layer . Due to the limited time, we made some simplifying assumptions in the specification of main functional modules as well as reduced the frame body data length to avoid huge labor of layout and testing. Table_1 shows some basic features for the final chip.

Table 1. Basic chip features