Stimulus file for calculating Frame Check Sequence field

// CRC_5 Verilog stimulus file.

initial
begin

$monitor ($time, "clk=%b, clr=%b, PHY_in=%b, r=%b", clk, clr, PHY_in, r);

clk = 1'b0;
clr = 1'b0;
PHY_in = 4'b0000;
#5 clr=1;

//Frame Control

#5 PHY_in[3:0] = 4'b0001; //protocol=00; type=00;
#10 PHY_in[3:0] = 4'b1101; //subtype=1101;
#10 PHY_in[3:0] = 4'b1000; //tofrom=10; MoreFrag=0; Retry=0;
#10 PHY_in[3:0] = 4'b0011; //PwrMgmt=0; MoreDate=0; WEP=1; order=1;

//Duration/ID

#10 PHY_in[3:0] = 4'b0000;
#10 PHY_in[3:0] = 4'b1101;
#10 PHY_in[3:0] = 4'b0001;
#10 PHY_in[3:0] = 4'b1101;

//Address 1

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

// end of data to be transmitted //

#25 $finish;

end

initial
begin

forever
#5 clk=~clk;

end
 

Frame Check Sequence field result

Simulation for the whole chip

// MAC_5 Verilog stimulus file.
// Author: Yiling Zhang.
// Last modification: 04:07 Nov 30, 2006.

initial
begin

PHY_go = 1'b0;
PHY_in[3:0] = 4'b0000;

#5 PHY_go = 1'b1;

//Frame Control

#5 PHY_in[3:0] = 4'b0001; //protocol=00; type=00;
#10 PHY_in[3:0] = 4'b1101; //subtype=1101;
#10 PHY_in[3:0] = 4'b1000; //tofrom=10; MoreFrag=0; Retry=0;
#10 PHY_in[3:0] = 4'b0011; //PwrMgmt=0; MoreDate=0; WEP=1; order=1;

//Duration/ID

#10 PHY_in[3:0] = 4'b0000;
#10 PHY_in[3:0] = 4'b1101;
#10 PHY_in[3:0] = 4'b0001;
#10 PHY_in[3:0] = 4'b1101;

//Address 1

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

#10 PHY_in[3:0] = 4'b1010; // \
#10 PHY_in[3:0] = 4'b1101; // Address1=4'hADD1
#10 PHY_in[3:0] = 4'b1101; //
#10 PHY_in[3:0] = 4'b0001; // /

//Frame Check Sequence

#10 PHY_in[3:0]=4'b1111;
#10 PHY_in[3:0]=4'b1110;
#10 PHY_in[3:0]=4'b0100;
#10 PHY_in[3:0]=4'b0010;

#10 PHY_in[3:0]=4'b0010;
#10 PHY_in[3:0]=4'b1011;
#10 PHY_in[3:0]=4'b1111;
#10 PHY_in[3:0]=4'b1010;

// end of data stream //

#75 $finish;

end

initial
begin
clk=0;

forever
#5 clk=~clk;
end