Chip Architecture

Architecture

The IEEE 802.11 Receiver MAC Layer provides functionality to allow reliable data delivery to the Logical Link Control (LLC) layer from the Physical layer (PHY). Five decoder block( Frame Control Decoder, Frame Control Decoder, Duration/ID Decoder, Address Decoder, Sequence Control Decoder, Frame Body Decoder) are implemented to decode the corresponding frame sub-fields. The data interface and working sequence control are provided by the Decoder Controller. The data delivery itself is based on an asynchronous, best-effort, connectionless delivery of MAC layer data. There is no guarantee that the frames will be delivered successfully. Therefore, error detection module based on Cyclic Redundancy Check is adopted to achieve the conversion of potentially unreliable physical link between two machines into an apparently very reliable link. Figure 1 shows the architecture block diagram. Brief function description for each main blocks is given in Table 1. For detailed function specification and implemented algorithm please refer to Chip Modules.

Figure 1. IEEE 802.11 Receiver MAC Layer architecture block diagram

Table 1. Block function specification

Block Name	Brief Description
Decoder Controller	Brings data in from the PHY Layer, 4 bits at a time, and creates a 16-bit internal word. Controls data-shift, creat decoder working clock on new word, and passes received 16-bit word to one of the decoder blocks selected.
Frame Control Decoder	Decodes information in the Fame Control word field, extracting relevant information. Feed back frame subtype and tofrom fields to decoder controller.
Duration/ID Decoder	Decodes the information of duration time that the medium is expected to remain busy for the transmission currently in progress.
Address Decoder	Decodes MAC address information.
Sequence Control Decoder	Decodes frame numbers and fragment numbers in Data frames.
Frame Body Decoder	Decode the frame body and extracted data information..
Frame Check Sequence	Brings data in from the PHY Layer, 4 bits at a time, check the reliability of frame data by adopting fast parallel Cyclic Redundancy Check.