Building_blocks

Key building blocks

	Schematic View	Verilog-XL Simulation	Spectre_S Simulation	Layout View	DRC	Extracted View	LVS	Post-layout Simulation
Not			√	√	√	√	√	√
Buffer			√	√	√	√	√	√
And2			√	√	√	√	√	√
NAND2			√	√	√	√	√	√
NAND3			√	√	√	√	√	√
NAND4			√	√	√	√	√	√
NOR2			√	√	√	√	√	√
OR2			√	√	√	√	√	√
XOR			√	√	√	√	√	√
Half-Adder				√	√	√	√
3:2 compressor or Full-Adder				√	√	√	√
Bistable D Latch				√	√	√	√
D flip-flop				√	√	√	√
Transmission Gate				√	√	√	√
8-bits register				√	√	√	√
Booth-Encoder				√	√	√	√
2's complement generator				√	√	√	√
one partial product generator				√	√	√	√
8 Partial Product Generator				√	√	√	√
p0 sign extension				√	√	√	√
p1 sign extension				√	√	√	√
p2 sign extension				√	√	√	√
p3 sign extension				√	√	√	√
p4 sign extension				√	√	√	√
p5 sign extension				√	√	√	√
p6 sign extension				√	√	√	√
p7 sign extension				√	√	√	√
4:2 compressor				√	√	√	√
4-bit generate and propagate circuit				√	√	√	√
4-bit look-ahead carry generator				√	√	√	√
4-bit sum generator				√	√	√	√
16-bit Carry Look-Ahead Adders				√	√	√	√
Wallace Tree				√	√	√	√
Wallace Tree and CLA				√	√	√	√
8*8 bit Multiplier				√	√	√	√	√

Delay of key building blocks

Two good 4:2 compressor result in bad Wallace tree