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In this project, we are
planning to build a Booth Encoded Wallace-tree multiplier. Multipliers are
one of the most important parts in signal processing or other
computationally intensive applications. Therefore, designing multipliers
that are high-speed, low power, and/or regular in layout are of substantial
research interest. Many attempts have been made to reduce the number of
partial products generated in a multiplication process by using the modified
Booth algorithm. Moreover, Wallace Tree CSA structures have been used to sum
the partial products in reduced time. In this regard, when both algorithms
are combined in one multiplier, we can expect a significant reduction in
computing multiplications. Our goal is to reduce computation time by
using Booth's algorithm for multiplication and to
reduce chip area by using Carry Save Adders arranged in a Wallace tree
structure.
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Fabrication Process |
AMI 0.6u C5N |
| Final
Chip Area |
4.2mm*1.5mm |
| Number of
PMOS |
3040 |
| Number of
NMOS |
3040 |
| Total
number of Transistors |
6080 |
| Speed |
20 MHz |
| Power
Dissipation |
15.14 mW |
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