Design Team


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Design Team
Introduction
4*4 multiplier
Chip Architecture
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Chip Implementation
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Nahid Rahman

 

              PhD student

              Contact Info:             

             Halligan Hall, Room 137  

              161 College Avenue,     

              Medford, MA 02155              

              email: Nahid.Rahman@tufts.edu        

http://www.eecs.tufts.edu/~nrahma01/index.htm
 

 

Ruida Yun

 

 

PhD student 

Office:
Room 137 F
Halligan Hall
Tufts University
Medford, MA
02155

email: Ruida.Yun@tufts.edu

http://www.eecs.tufts.edu/~ryun01/index.htm

   
 

Team Management Plan

The project was divided into two main parts. The first part is using Booth's algorithm to recode the multiplier and generate the partial products. The second part is using the Wallace method to generate the final output.

  Responsibilities Task Description

 Contributions

Nahid Booth's Algorithm

Encode the multiplier and

generate the partial products

using the booth algorithm

 

8 Bit Register

2's Complement Generator

Booth Encoder

Sign Extension Modules

Partial Products Generator

Ruida Yun Wallace Tree

Reduce the partial product

 and add them together

 using Wallace tree

 

Full-Adder

4:2 Compressor

4-bit Look-ahead Carry Generator

4-bit Generate and Propagate Circuit

4-bit Sum Generator

16-bit Carry Look-Ahead Adders

Wallace Tree