Chip Implementation


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Introduction
4*4 multiplier
Chip Architecture
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Chip Implementation
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  • Symbol
  • Schematic
  • Layout
  • DRC
  • LVS
  • Extracted view
  • Verilog_XL simulation
  • Spectre_S simulation
  • Post_layout simulation
  • Power dissipation

Symbol

Schematic

Layout

DRC

Extracted View

LVS result (outfile)

Verilog_XL simulation

Spectre_s Simulation     pdf

Post_layout Simulation  pdf

Power Dissipation

The average current from calculator is 5.14mA, so the power dissipation is P=5.14 mA * 3 V=15.14 mW.