Current Projects
Application-driven non-volatile memory design

The “memory wall” problem has emerged as one of the main energy bottlenecks in many data-intensive applications (e.g. deep neural networks (DNNs) and graph processing). Emerging non-volatile memory technologies are a promising solution for implementing dense, energy-efficient on-chip memories. However, these new technologies are often limited by their programming performance and reliability. In this project, we investigate the interplay between NVM device characteristics, programming schemes, and memory array architectures to expose different design choices with the goal of optimizing performance, energy, area, and accuracy metrics for data-intensive workloads.

Energy-efficient hardware for multi-task edge inference

Multi-task deep learning models have become a popular approach for reducing redundancy in computations as well as parameters storage for correlated tasks. Nonetheless, these solutions alone are generally not sufficient for deploying multi-task models to resource-limited mobile hardware platforms. In this project, we expore several hardware/software co-design optimizations such as model compression techniques combined with dense embedded non-volatile memories. We evaluate trade-offs between model compression and multi-task capabilities for different application scenarios (computer vision, natural language processing). The goal is to expose and employ principled co-design optimizations to enable robust multi-task learning on resource-constrained mobile hardware platforms.

Heterogeneous SoC design for Edge/IoT

Modern system-on-chip (SoC) architectures for Internet-of-Things (IoT) devices need to operate on wide range of power modes. Heterogeneous SoC architectures integrating a variety specialized hardware blocks help strike a balance between flexibility and low-power operation across several compute kernels. As a part of this project, we investigate how emerging technologies can help designers implement more energy-efficient designs. Through this process we also identify design methodologies and best practices for agile chip design.