Leading One Detector Circuit:
The 16-bit Leading One Detector Circuit is a serial/parallel circuit. The 16-bit input data is split into groups of 4 bits. These set of four 4-bit inputs are input to four 4-input OR gates, followed by a serial combinational logic which determines the group that has the leading one. The 16-bit input is fed in parallel to another set of 4-bit Leading One Detector circuits, which determine the position of leading one in each set of 4-bit inputs. The output of the first stage LOD circuit acts as control signals which control 4 select lines to four groups of 4-bit MUX, housed in the second LOD stage (schematic). Only one select line is HIGH to allow a 4-bit MUX to pass the 4-bit decoded word that has the leading one. The circuit generates a 16-bit active-high decoded binary word that has only one high bit, corresponding to the leading one.
The simulation results of LOD 4-bit and LOD-group are shown below:
LOD 4-bit
| G3 |
G2 |
G1 |
G0 |
S |
Time Delay (ns) |
| 1 |
1 |
1 |
1 |
0 -> 1 |
0.305 see plot |
| 0 |
0 |
0 |
0 -> 1 |
0 -> 1 |
0.41 see plot |
| 0 |
0 |
0 |
1 |
0 -> 1 |
0.373 see plot |
LOD-group:
| G3 |
G2 |
G1 |
G0 |
Time Delay (ns) |
| 0 -> 1 |
0 -> 1 |
0 -> 1 |
1 |
1.061 see plot |
| 0 |
0 |
0 -> 1 |
0 -> 1 |
1.607 see plot |
| 0 |
0 -> 1 |
1 |
0 -> 1 |
1.329 see plot |
| 0 |
0 -> 1 |
0 -> 1 |
0 -> 1 |
1.426 see plot |
| 0 -> 1 |
0 |
0 |
0 -> 1 |
1.483 see plot |
For the logarithmic converter, this block is the most important block and has the highest delay. So, in order to reduce the increase the throughput of the circuit, we attempted pipelining in this circuit by placing four 4-bit registers before the second stage of LOD circuit. In such a configuration, the 4-bit registers included an active low Clear signal and the output of the 1st stage was used as control signal for the Clear input, such that the registers only passed the 4-bits of the group with the leading one. However, the setup time and propagation delay of the register added upto 1 ns and the total simulated delay for this block is slightly more than 2 ns, so we do not gain much in a 16-bit LOD by incorporating pipelining technique. However, it will definitely increase the speed of operation for circuits with higher number of inputs. Simulation reults of LOD circuit are shown below:
16 word by 4 bit NOR ROM:
The active high decoded output from the leading one detection circuit is fed to a 16 word by 4 bit NOR ROM which consists of a combination of bit lines, PMOS pull-up and NMOS pull-downs, constituting a pseudo-NMOS NOR gate with the word lines as inputs. Under normal operating conditions, only one of the word lines goes high, and at most, only one of the pull-down devices is turned ON. This raises some interesting issues regarding the size of both the cell and pull-up transistors, as discussed below:
- To keep the cell size and the bit line capacitance small, the pull-down device should be kept as low as possible to the minimum size.
- The resistance of the pull-up device must be larger than the pull-down resistance to ensure an adequate low-level.
The simulated propagation delay for this block is 0.563 ns and it is the same for all inputs.
Logarithmic Shifter:
The logarithmic shifter performs shifting in stages. The total shift value is decomposed into shifts over the powers of two. A shifter with a maximum shift width of M consists of log2M stages, where the ith stage either shifts over 2i or passes the data unchanged. In our design, we have incorporated a 16-bit shifter with 4 stages. However, we are using only 15 bits since the 16th bit is redundant for the design.
The speed of the logarithmic shifter depends on the shift width in a logarithmic way. In our case, we use the 4-bit encoded output of the previous Leading One Detector stage as the control signal for the shifter. The 15-bit input is present before the control signal arrives. So the largest delay occurs when all the 4-bits of the control signal change. Again if control changes from 1110 to 0001, the MSB traverses down from top to bottom. So this corresponds to the longest path in the circuit.
16-bit binary to binary Logarithmic Converter:
This block is implemented by integrating the above blocks. The output from the shifter stage forms the mantissa of the logarithm and the output of the Leading One Detection circuit is the characteristic. We use separate 4 bit registers and 12 bit registers to store the characteristic and mantissa respectively. (Please note that here we are truncating the 3 LSBs of the shifter output, so this incorporates a truncation error in the circuit). Simulation results are shown below:
Logarithmic Converter 1 --character part
Logarithmic Converter 1 --mantissa part
The 16-bit input is 0000 0110 0011 1100, which corresponds to 1596 in decimal. The logarithm base-2 value of 1596 is 10.64
The output of the logarithmic converter is 1010.1000111100, which corresponds to 10.559 in decimal.
Logarithmic Converter 2 --character part
Logarithmic Converter 2 --mantissa part
The 16-bit input is 1011 1011 0001 1000, which corresponds to 31512 in decimal. The logarithm base-2 value of 31512 is 14.9436
The output of the logarithmic converter is 1111.011101100011, which corresponds to 15.461 in decimal.
Here, we observe a relatively large error in the output. This is because of the approximation we have assumed in calculating the logarithm to the base of the input number. We assume the decimal part m (after the leading '1' ) to be very small and ignore the higher orders of m. However, in this case, the value of higher orders of m plays a significant role in determining the output value, thus resulting in a significant error.
