Simulation for 16-bit Divider
 
Divisor Shifter : Divisor Shifter is used to normalize the divisor. All incoming divisors that are less than 8 should be shifted and normalized from 8~15, this is to reduce the number of iterations of division and increase the speed of the divider. The basic functions of divisor shifter are: A. Output normalized divisor; B. Give out the number of bits by which the divisor has been shifted. (see simulation results)
 

Remainder Selector : A remainder selector is needed to determine the output of the 4-bit subtractor,:if the partial dividend is larger than the normalized divisor, the output of subtractor should be equal to the difference between partial dividend and normalized divisor; if not, the subtractor just pass the partial dividend through to the next iteration. (simulation results for Remainder Selector can be found here)

 

4_bit_controlled_subtractor: The 4_bit_controlled_subtractor is the building block of this divider, its behaviour efftets the verall performance of the divider. Each stage of 4_bit_controlled_subtractor outputs one-bit of quotient and 4-bit remainder, a total of 13 subtractors are needed to obtain a 13-bit partial quotient. Partial quotient togethe with the output of comparator are then processed by the Quotient Shifter. Simulation results of 4-bit subtractor can be found here.

 
Quotient Shifter : Quotient shifter that is used in this divider is actually a set of 2-1 MUX that performs 1-bit shift. The direction of shift is controlled by the output of Divisor Shifter. Simulation result can be found here.
 

Comparator: The function of comparator is to compare the final 4-bit remainder with the original divisor (unshifted) and to calibrate the quotient. Since all divisors are normalized from 8~15, it is very likely that the remainder is larger than the unshifted divisor, under such circumstances, we need to add a "one" to the end of the partial quotient to eliminate error, this is done by the comparator. Simulation result of comparator can be found here.

 
Completed Divider: Based on restoring division algorithm, this divider takes 13 iterations to complete a division. Special effort has been put on resizing the tansistors and improving the algorithm to decrease the propagation delay. However, due to hardware complexity and limitation of restoring division algorithm ifself, a general of 30ns delay is showed from the simulation result. Simulation for complete divider can be found here.