NOT:

A simple CMOS inverter is used. The DC characteristics of the inverter has been plotted.

Here, tplh stands for the propagation delay when output goes from low to high and tphl stands for the propagation delay when output goes from high to low.

The simulation of the basic logic gates are shown below:

NOT (VDC) :

NOT (high-to-low) :

NOT( low-to-high ) :

NAND-2(high-to-low):

NAND-2 (low-to-high):

NOR-3 (high-to-low) :

NOR-3 (low-to-high) :

For all the basic gates, we consider the change of input at the critical transistors, which is the pmos or nmos whose drain is directly connected to the output node.

Let tplh be the propagation deley from low-to-high and tphl the propagation from high-to-low, we have the following table:

MUX:

The 2:1 MUX is a major block of the design as it is used at several places in the higher levels. So special attention has been paid to reduce the delay and power consumption of this block.

We do not use a MUX designed using CMOS logic because it is very slow. So, we use a MUX built using pass transistor logic. We can either use one NMOS transistor as the selection switch or a Transmission Gate (TG) as the switch. The problem with using NMOS transistor as the selection switch is that it cannot charge up the internal node before the output inverter to Vdd. So, we use a TG as the selection switch in the design of our MUX.

There are two important timing parameters in a MUX design: the D-Q delay and the C-Q delay. The D-Q delay is defined as the propagation delay from the input transition to the resulting output transition while the control signals remain unchanged. The C-Q delay is defined as the propagation delay from the change of the control signals to the resulting output transition while the inputs stay the same.

The following table shows the simulation result for C-Q delay.

We observe that the worst case D-Q delay is 0.083 ns.

We observe that the worst case S-Q delay is 0.208 ns.

We get high delay for the case when A1=HIGH; A0=LOW and the control goes from LOW to HIGH because A1 is passed by a PMOS switch which is activated by Cbar, which in turn is affected by the delay of the NOT gate. Similar is the reason for high delay in the case when A1=HIGH; A0=LOW and the control goes from HIGH to LOW. Further, the delay in former case is higher since the signal passes through the slower PMOS.

MUX for DFF:

We have designed a separate MUX for the D Flip Flop, by putting inverters at various stages since we require a strong signal at the output node in case of a Flip Flop, otherwise it will not be able to hold and latch the signal.

The plot shows the simulation result for the worst case, showed in above case.

We observe that the worst case delay for the MUX is 0.379 ns.

D Flip Flop:

A multiplexer based positive edge-triggered latch is used in this particular implementation. On the low phase of the clock, the master stage is transparent, and the D input is passed to the master stage output. During this period, the slave stage is in the hold mode, keeping its previous value by using feedback. On the rising edge of the clock, the master stage stops sampling the input, and the slave stage starts sampling. During the high phase of the clock, the slave stage samples the output of the master stage while the master stage remains in a hold mode. Since the output of the master stage is constant during the high phase of the clock, the output Q makes only one transition per cycle. The value of Q is the value of D right before the rising edge of the clock, thus achieving the positive edge-triggered effect.

The Flip Flops are characterized by three important timing parameters: the setup time, tsu; the hold time, th and the propagation delay, td.

Set-up time:

The setup time is the time before the rising edge of the clock that the input data D must be valid. If we look into the circuit, it is observed that the setup time is equal to the sum of 3 times the propagation delay of the inverter and the propagation delay of the transmission gate.

To obtain the setup time of the flip-flop, we progressively skew the input with respect to the clock edge until the circuit fails. If we observe the simulation plot, we see that the if the clock is skewed by 460 ps with respect to the input, the wrong signal travels to the output, but if we increase the skew to 470 ps, we get correct signal at the output. Hence, setup time for the flip-flop is 470 ps.

Plot for 460ps

Plot for 470ps

Propagation Delay

The propagation delay is the time it takes for the output to appear after the clock rises. In our design it is equal to the sum of the delay of the inverter and the transmission gate.

The simulated propagation delay for the circuit is 0.589 ns.

Hold Time:

The hold time is the time that the input must be kept stable after the rising edge of the clock. The hold time for this configuration of D Flip-flop is zero, which is proved by the simulation result shown.