Clocked Counters
To solve the problems of propagation delay introduced by the ripple counter, we'll use a synchronized counter. The synch'd counters are set up so that one clock pulse drives every stage. Since synch counters are readily available as cheap IC's, we'll move straight on to talk about how to use a counter chip.
A counter chip comes with a fair number of features on it. Here's the pinout for a 74HC193, which is a 4-bit binary up/down counter with load and clear.
Let's have a look at the different pins.
UP and DOWN. This counter chip has two clocks, UP and DOWN. When UP gets a rising edge clock pulse, it makes the internal flops count up by one number. When the DOWN pin gets a rising edge clock pulse, the flops count down by one number. If you're going to only use one clock pin, tie the other to ground.
Qa, Qb, Qc, and Qd. These are the four output pins. Qa is the low order bit, Qd is the high order bit.
BO' and CO'. These pins stand for Borrow Out and Carry Out, respectively. They signal when the counter is about to reset. We can chain several of these counters together, by having the BO' pin drive the next counter's DOWN clock, and the CO' pin driving the next counter's UP clock.
CLR. This is a Clear pin, which will instantly reset all the outputs to LOW, or 0.
LOAD'. The LOAD' pin tells the chip to LOAD the data from pins A through D into outputs Qa to Qd on the next clock pulse. This allows us to start counting from a number other than zero.
A, B, C, D. These four pins accept the input data, if we wish to set the counter to a certain number using the LOAD' pin.
As always, it's a good idea to tie any input pins we don't want to use to GND.
As we mentioned, we can chain a series of counters together to form one big counter capable of handling as many digits as we like:
Which of the Q's is the low order bit for the counter-system? Which of the Q's is the high order bit?